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APPENDIX
Table A.8-9 6 Logic 2 instructions (long word)
Mnemonic
ANDL
A,ear
2
ANDL
A,eam
2+
ORL
A,ear
2
ORL
A,eam
2+
XORL
A,ear
2
XORL
A,eam
2+
Note:
See Table A.5-1 "Execution cycle counts in each addressing mode" and Table A.5-2 "Cycle count
correction values for counting execution cycles" for information on (a) to (d) in the table.
Table A.8-10 6 Sign inversion instructions (byte, word)
Mnemonic
NEG
A
1
NEG
ear
2
NEG
eam
2+
NEGW
A
1
NEGW
ear
2
NEGW
eam
2+
Note:
See Table A.5-1 "Execution cycle counts in each addressing mode" and Table A.5-2 "Cycle count
correction values for counting execution cycles" for information on (a) to (d) in the table.
Table A.8-11 1 Normalization instruction (long word)
Mnemonic
NRML
A,R0
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
648
#
RG
B
6
2
0
long (A) <-- (A) and (ear)
7+(a)
0
(d)
long (A) <-- (A) and (eam)
6
2
0
long (A) <-- (A) or (ear)
7+(a)
0
(d)
long (A) <-- (A) or (eam)
6
2
0
long (A) <-- (A) xor (ear)
7+(a)
0
(d)
long (A) <-- (A) xor (eam)
#
RG
B
2
0
0
byte (A) <-- 0 - (A)
3
2
0
byte (ear) <-- 0 - (ear)
5+(a)
0
2 x (b)
byte (eam) <-- 0 - (eam)
2
0
0
word (A) <-- 0 - (A)
3
2
0
word (ear) <-- 0 - (ear)
5+(a)
0
2 x (c)
word (eam) <-- 0 - (eam)
#
RG
B
2
*1
1
0
long (A) <-- Shifts to the position where '1' is set for
the first time.
byte (RD) <-- Shift count at that time
Operation
L
H
-
-
-
-
-
-
Operation
L
H
X
-
-
-
-
-
Operation
L
H
-
A
I
S
T
N
Z
V
C
H
-
-
-
-
*
*
R
-
-
-
-
-
*
*
R
-
-
-
-
-
*
*
R
-
-
-
-
-
*
*
R
-
-
-
-
-
*
*
R
-
-
-
-
-
*
*
R
-
A
I
S
T
N
Z
V
C
H
-
-
-
-
*
*
*
*
-
-
-
-
*
*
*
*
-
-
-
-
*
*
*
*
-
-
-
-
*
*
*
*
-
-
-
-
*
*
*
*
-
-
-
-
*
*
*
*
A
I
S
T
N
Z
V
C
H
-
-
-
-
-
*
-
-
R
M
W
-
-
-
-
-
-
R
M
W
-
-
*
-
-
*
R
M
W
-
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