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I List of Registers and Reset Values of 16-bit Input/Output Timer
Figure 7.3-1 List of Registers and Reset Values of 16-bit Input/Output Timer
Timer counter control status register
(TCCS)
Timer counter data register upper
(TCDT: H)
Timer counter data register lower
(TCDT: L)
Input capture control status
register(ICS01)
Input capture data register 0
upper (IPCP0: H)
Input capture data register 0
lower (IPCP0: L)
Input capture data register 1
upper (IPCP1: H)
Input capture data register 1
lower (IPCP1: L)
Input capture control status
register (ICS23)
Input capture data register 2
upper (IPCP2: H)
Input capture data register 2
lower (IPCP2: L)
Input capture data register 3
upper (IPCP3: H)
Input capture data register 3
lower (IPCP3: L)
: Undefined
bit
7
6
5
0
0
0
0
bit
15
14
13
12
0
0
0
0
7
6
5
bit
0
0
0
0
bit
7
6
5
0
0
0
0
15
14
13
12
bit
7
6
5
bit
15
14
13
12
bit
7
6
5
bit
bit
7
6
5
0
0
0
0
bit
15
14
13
12
bit
7
6
5
bit
15
14
13
12
7
6
5
bit
CHAPTER 7 16-bit I/O timer
4
3
2
1
0
0
0
0
0
11
10
9
8
0
0
0
0
4
3
2
1
0
0
0
0
0
4
3
2
1
0
0
0
0
0
11
10
9
8
4
3
2
1
0
11
10
9
8
4
3
2
1
0
4
3
2
1
0
0
0
0
0
11
10
9
8
4
3
2
1
0
11
10
9
8
4
3
2
1
0
227
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