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I ROM Area
G
Vector table area (address: FFFC00
• The vector table is provided for reset and interrupts.
• This area is allocated at the top of the ROM area. And The starting address of the corresponding
processing routine is set to the address of each vector table as data.
G
Program area (address: to FFFBFF
• ROM is contained as the internal program area.
• The capacity of the internal ROM depends on the product.
I RAM Area
G
Data area (address: 000100
• Static RAM is contained as the internal data area.
• The capacity of the internal RAM depends on the product.
G
General-purpose register area (address: 000180
• Auxiliary registers for operations or transfer of the 8-bit, 16-bit, or 32-bit data are allocated in this area.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
• When this area is used as general-purpose registers, they can be accessed quickly using a short
instruction through general-purpose register addressing.
G
Expanded intelligent I/O service (EI
• This area holds the transfer mode, I/O address, transfer count, and buffer address.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
I I/O Area
G
Interrupt control register area (address: 0000B0
The interrupt control registers (ICR00 to ICR15) correspond to all resources with an interrupt function, and
control the setting of interrupt level and EI
G
Resource control register area (address: 000020
This area controls the resource function and data I/O.
G
I/O port control register area (address: 000000
This area controls the I/O ports and data I/O.
I Extended I/O Area
G
Peripheral function control register area (address: 003900
This area controls the resource function and data I/O.
to FFFFFF
)
H
H
)
H
to 000900
)
H
H
to 00037F
H
2
OS) descriptor area (address: 000100
to 0000BF
H
2
OS.
to 0000AF
H
to 00001F
H
)
H
to 00017F
H
)
H
)
H
)
H
to 003FFF
)
H
H
CHAPTER 3 CPU
)
H
21
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