Program Example Of Delayed Interrupt Generation Module - Fujitsu MB90895 Series Hardware Manual

CHAPTER 11 Delayed interrupt generation module
11.6

Program Example of Delayed Interrupt Generation Module

This section gives a program example of the delayed interrupt generation module.
Program Example of Delayed Interrupt Generation Module
Processing specification
The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR)
to generate a delayed interrupt request and performs task switching.
Coding example
ICR15 EQU
DIRR EQU
DIRR_R0 EQU
;---------Main program------------------------------------
CODE CSEG
START:
AND
MOV
MOV
OR
SETB
LOOP MOV
MOV
BRA
;---------Interrupt program--------------------------------------
WARI:
CLRB
:
; User processing
; :
RETI
CODE ENDS
;---------Vector setting-----------------------------------------
VECT CSEG
ORG
DSL
ORG
DSL
DB
VECT ENDS
END
328
0000BFH
00009FH
DIRR:0
CCR,#0BFH
I:ICR15,#00H
ILM,#07H
CCR,#40H
I:DIRR_R0
A,#00H
A,#01H
LOOP
I:DIRR_R0
ABS=0FFH
0FF54H
WARI
0FFDCH
START
00H
START
;Interrupt control register
;Delay interrupt factor generating/
Release register
;Delay interrupt request generating bit
;Stack pointer (SP),already initialized
;Interrupt disabled
;Interrupt level 0 (storng)
;Setting ILM in PS to levle 7
;Interrupt enabled
;Delay interrupt request generating
;No limit roop
;Clear interrupt request flag
;Recovery from interrput
;Setting vector to interrupt #42 (2A
;Reset vector setting
;Setting to single chip mode
)
H