Fujitsu MB90895 Series Hardware Manual page 501

I CAN Controller Registers
Figure 16.3-1, Figure 16.3-2 and Figure 16.3-3 list the registers of the CAN controller.
CAN controller control register
bit15
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
bit15
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
: Resarved area is address for using in system, so it must not use.
Figure 16.3-1 Registers of CAN Controller (Control Registers)
bit8 bit7
TREQR (Transmission request register)
TCANR (Transmission cancel register)
TCR (Transmission completion register)
RCR (Reception completion register)
ROVRR (Reception overrun register)
RIER (Reception completion interrupt enable register)
bit8 bit7
CSR (Control status register)
RTEC (Transmission/reception error counter)
BTR (Bit timing register)
RFWTR (Remode frame reception waiting register)
TIER (transmission completion interrupt enable register)
AMSR (Acceptance mask select register)
Reserved area
AMR0 (Acceptance mask select register 0)
AMR1 (Acceptance mask select register 1)
BVALR (Message buffer valid register)
RRTRR (Reception RTR register)
LEIR (Last event display register)
IDER (IDE register)
TRTRR (Transmission RTR register)
CHAPTER 16 CAN controller
bit0 Reset value
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
bit0 Reset value
00XXX000 0XXXX001
B
000XX000
00000000 00000000
B
X1111111 11111111
B
XXXXXXXX
00000000
XXXXXXXX
00000000
XXXXXXXX XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
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