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CHAPTER 10 8/16-bit PPG timer
10.2.1
Block Diagram for 8-/16-bit PPG Timer 0
The 8-/16-bit PPG timer 0 consists of the following blocks.
I Block Diagram for 8-/16-bit PPG Timer 0
PRLH0
("H" level side)
PPG0 temporary
buffer 0 (PRLBH0)
Count starting
value
PPG0 down counter
-
: Unused
Reserved
: Reserved bit
HCLK
: Oscillation clock frequency
φ
: Machine clock frequency
*
:
The interrupt output of 8-/16-bit PPG timer 0 is combined to one interrupt by
OR circuit with the interrupt request output of PPG timer 1.
294
Figure 10.2-2 Block Diagram for 8-/16-bit PPG Timer 0
PPG0 reload
register
PRLL0
("L" level side)
Select signal
Reload register
L/H selector
Reload
Under flow
(PCNT0)
CLK
Time base timer output
(512/HCLK)
Peripheral clock (1/φ)
Peripheral clock (2/φ)
Peripheral clock (4/φ)
Peripheral clock (8/φ)
Peripheral clock (16/φ)
PPG0 operating mode control register
(PPGC0)
PEN0
-
PE0 PIE0 PUF0
Clear
Pulse selector
PPG0
output latch
Inversion
Count
clock
selector
3
Select signal
PCS2
PCS1
PCS0 PCM2 PCM1 PCM0
PPG0/1 count clock select register (PPG01)
"H" level side data bus
"L" level side data bus
-
-
Reserved
Interrupt
request
R
output
S
Q
2
Operating mode
control signal
PPG1 under flow
PPG0 under flow
(to PPG1)
Pin
PPG0
PPG output control circuit
-
-
*
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