Fujitsu MB90895 Series Hardware Manual page 515

I Calculation of Bit Timing
Figure 16.3-12 and Figure 16.3-13 show the calculation example of bit timing, respectively, assuming input
clock (CLK), time quantum (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segment 1, 2
(TSEG1, TSEG2), re-synchronous jump width (RSJW), frequency divided (PSC).
•
TQ = (PSC + 1)
•
BT = SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 + 1) )
= (3 + TS1 + TS2)
•
RSJW = (RSJ + 1)
For each segment, the following conditions shoud be met.
•
When PSC is 1 to 63 (2 to 64-devided clock)
≥
TSEG1
≥
TSEG1
≥
TSEG2
≥
TSEG2
•
When PSC is 0 (1-devided clock)
≥
TSEG1
≥
TSEG2
≥
TSEG2
Figure 16.3-12 Calculation of Bit Timing
×
CLK
×
TQ
×
TQ
×
TQ
2TQ
RSJW
2TQ
RSJW
5TQ
2TQ
RSJW
CHAPTER 16 CAN controller
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