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CHAPTER 14 UART0
14.2
Block Diagram of UART0
The UART0 consists of the following block.
I Block Diagram of UART0
Dedicated
baud rate
generator
16-bit
reload timer
Pin
SCK
Pin
SIN
Reception state
judge circuit
Serial
edge
select
register
384
Figure 14.2-1 Block Diagram of UART0
Control bus
Clock
Reception
selector
clock
Start bit
detection circuit
Reception bit
counter
Reception parity
counter
Shift register
for reception
Serial input
data register
Internal data bus
Communi
MD
-cation
prescaler
DIV3
control
DIV2
DIV1
register
NEG
DIV0
Transmission
clock
Reception
control
cirsuit
Transmission
start circuit
Transmission
bit counter
Transmission
parity counter
Shift register
for transmission
Reception
complete
Serial outpu
data register
MD1
MD0
Serial
Serial
CS2
CS1
control
mode
CS0
register
register
SCKE
SOE
Reception
interrupt
request output
Transmission
interrupt
request output
Transmission
control
circuit
Pin
SOT
Transmission
start
Reception error
generating signal
2
for EI
OS (to CPU)
PEN
PE
P
ORE
Serial
SBL
FRE
CL
RDRF
status
A/D
TDRE
register
REC
RXE
RIE
TXE
TIE
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