Table of Contents
Advertisement
13.3.2
A/D Control Status Register (Low) (ADCS: L)
The A/D control status register (Low) (ADCS: L) provides the following settings:
• Selecting A/D conversion mode
• Selecting start channel and end channel of A/D conversion
I A/D Control Status Register (Low) (ADCS: L)
7
6
5
R/W
R/W
R/W
R/W
: Read/Write
: Reset value
Figure 13.3-3 A/D Control Status Register (Low) (ADCS: L)
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
bit2
ANE2
bit5
ANS2 ANS1 ANS0
bit7
MD1
Reset value
00000000
B
bit1
bit0
A/D conversion finish channel select bit
ANE1
ANE0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
bit4
bit3
A/D conversion start channel select bit
No start-up
state
0
0
0
AN0 pin
0
0
1
AN1 pin
0
1
0
AN2 pin
0
1
1
AN3 pin
1
0
0
AN4 pin
1
0
1
AN5 pin
1
1
0
AN6 pin
1
1
1
AN7 pin
bit6
A/D conversion mode selection bit
MD0
0
0
Single conversion mode 1 (enable to restart-up during operation)
0
1
Single conversion mode 2 (disable to restart-up during operation)
1
0
Sequential conversion mode (disable to restart-up during operation)
1
1
Stop conversion mode (disable to restart-up during operation)
CHAPTER 13 8/10-bit A/D converter
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
Read during
Read in
a pause in stop
cenversion
conversion mode
Channel
Channel number
just previously
number in
conversion
converted
359
Advertisement
Table of Contents
