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CHAPTER 16 CAN controller
Table 16.3-14 Functions of Transmission Complete Register (TCR)
bit0
to
bit7
512
Bit name
TC7 to 0:
These bits indicate whether the message buffer (x) completes
Transmission complete
transmitting message.
bits 7 to 0
When message transmitting completed: 1 is set to the TCx bit
corresponding to the message buffer (x) that completes
transmitting.
When set to 0: Clears bits if transmitting already completed
When set to 1: No effect
Read using read modify write instructions: 1 always read
•
•
Generation of transmission complete interrupt
•
Function
Setting the TCx bit when transmitting is completed (TCx =
1) overrides clearing of the TCx bit when 0 is written (TCx =
0) if both occur at the same time.
When the TREQx bit in the transmit request register
(TREQR) is set (TREQR: TREQx = 1), the TCx bit is
cleared (TCx = 0).
If the transmit complete interrupt enable register (TIER) is
set (TIER: TIEx = 1), a transmit complete interrupt is
generated when transmitting is completed (TCR: TCx = 1).
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