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16.3.12
Transmit complete register (TCR)
The transmission complete register (TCR) indicates whether a data transmission from
the message buffer completes.When an output of interrupt is enabled at completing
transmitting, an interrupt request is output when transmission is completed.
I Transmit complete register (TCR)
7
6
5
R/W
R/W
R/W
R/W
: Read/Write
: Reset value
Figure 16.3-20 Transmit complete register (TCR)
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
bit0
TC0
bit1
TC1
bit2
TC2
bit3
TC3
bit4
TC4
bit5
TC5
bit6
TC6
bit7
TC7
Reset value
00000000
B
Transmission complete bit 0 (message buffer 0)
Not Transmitting complete / Not transmission
0
1
Transmitting complete
Transmission complete bit 1 (message buffer 1)
Not Transmitting complete / Not transmission
0
1
Transmitting complete
Transmission complete bit 2 (message buffer 2)
Not Transmitting complete / Not transmission
0
1
Transmitting complete
Transmission complete bit 3 (message buffer 3)
Not Transmitting complete / Not transmission
0
1
Transmitting complete
Transmission complete bit 4 (message buffer 4)
Not Transmitting complete / Not transmission
0
1
Transmitting complete
Transmission complete bit 5 (message buffer 5)
Not Transmitting complete / Not transmission
0
1
Transmitting complete
Transmission complete bit 6 (message buffer 6)
0
Not Transmitting complete / Not transmission
1
Transmitting complete
Transmission complete bit 7 (message buffer 7)
Not Transmitting complete / Not transmission
0
1
Transmitting complete
CHAPTER 16 CAN controller
511
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