Standby Mode - Fujitsu MB90895 Series Hardware Manual

CHAPTER 3 CPU
3.8.5

Standby Mode

The standby mode causes the standby control circuit to either stop supplying an
operation clock to the CPU and resources, or to stop the oscillation clock (HCLK) to
reduce power consumption.
I the operating state in each standby mode
Table 3.8-3 shows the operating state in each standby mode.
Table 3.8-3 the operating state in each standby mode
Mode Name
Sleep Main sleep
mode mode
Sub-sleep
mode
PLL sleep
mode
timebase SPL=0
timer
mode
SPL=1
watch SPL=0
mode
SPL=1
stop SPL=0
mode
SPL=1
134
Transition Oscillation
clock
conditions
(HCLK)
(SCLK)
MCS=1
SCS=1
SLP=1
MCS=X
×
SCS=0
SLP=1
MCS=0
SCS=1
SLP=1
MCS=X
SCS=1
TMD=0
MCS=X
SCS=1
TMD=0
MCS=X
SCS=0
TMD=0
MCS=X
SCS=0
TMD=0
STP=1
STP=1
Sub Machine CPU
clock
clock
Resource pin Setting disabled
external reset or
interrupt
external reset or
interrupt
external reset or
interrupt
external reset or
*1
interrupt
external reset or
Hi-Z
*1
interrupt
*3
external reset or
*2
interrupt
external reset or
Hi-Z
*2
interrupt
*3
external reset or
interrupt
external reset or
Hi-Z
*3
interrupt
*4
*4
*5
*5
*6
*6