Block Diagram Of 8-/10-Bit A/D Converter - Fujitsu MB90895 Series Hardware Manual

13.2

Block Diagram of 8-/10-bit A/D Converter

The 8-/10-bit A/D converter consists of following blocks.
I Block Diagram of 8-/10-bit A/D Converter
A/D control
status
register
(ADCS)
BUSY
ADTG
TO
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
A/D data
register
S10
(ADCR)
TO : Internal timer output
- : Unused
Reserved : Be sure to set to "0".
φ
: Machine clock
Figure 13.2-1 Block Diagram of 8-/10-bit A/D Converter
Interrupt requext output
INT INTE PAUS STS1 STS0 STRT
2
Start-up
selector
φ
Sample &
hold circuit
Analog
channel
selector
2
2
ST1 ST0 CT1 CT0 - D9 D8
Re-
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
served
2
Decoder
Comparator
AVR
AVcc
D/A converter
AVss
D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 13 8/10-bit A/D converter
6
Control circuit
351