Transmit Request Register (Treqr) - Fujitsu MB90895 Series Hardware Manual

16 bit, controller manual
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16.3.8

Transmit request register (TREQR)

The transmission request register (TREQR) sets a transmit request for each message
buffer and indicates its status.
I Transmit request register (TREQR)
7
6
5
R/W
R/W
R/W
R/W
: Read/Write
: Reset value
Figure 16.3-16 Transmit request register (TREQR)
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
bit0
TREQ0
bit1
TREQ1
bit2
TREQ2
bit3
TREQ3
bit4
TREQ4
bit5
TREQ5
bit6
TREQ6
bit7
TREQ7
Reset value
00000000
B
Transmission request bit 0 (message buffer 0)
Not request transmission (When reception no request transmission)
0
1
Transmit repuest (When reception transmit request)
Transmission request bit 1 (message buffer 1)
0
Not request transmission (When reception no request transmission)
1
Transmit repuest (When reception transmit request)
Transmission request bit 2 (message buffer 2)
0
Not request transmission (When reception no request transmission)
1
Transmit repuest (When reception transmit request)
Transmission request bit 3 (message buffer 3)
0
Not request transmission (When reception no request transmission)
1
Transmit repuest (When reception transmit request)
Transmission request bit 4 (message buffer 4)
0
Not request transmission (When reception no request transmission)
1
Transmit repuest (When reception transmit request)
Transmission request bit 5 (message buffer 5)
0
Not request transmission (When reception no request transmission)
1
Transmit repuest (When reception transmit request)
Transmission request bit 6 (message buffer 6)
0
Not request transmission (When reception no request transmission)
1
Transmit repuest (When reception transmit request)
Transmission request bit 7 (message buffer 7)
0
Not request transmission (When reception no request transmission)
1
Transmit repuest (When reception transmit request)
CHAPTER 16 CAN controller
503

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