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CHAPTER 12 DTP/external interrupt
G
DTP/external interrupt input detector
This circuit detects interrupt requests or data transfer requests generated from external peripheral devices.
The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting
register (ELVR) is detected is set to 1 (EIRR: ER).
G
Detection level setting register (ELVR)
This register sets the level or edge of input signals from external peripheral devices that cause DTP/external
interrupt factors.
G
DTP/external interrupt factor register (EIRR)
This register holds DTP/external interrupt factors.
If an enable signal is input to the DTP/external interrupt pin, the corresponding DTP/external interrupt
request flag bit is set to "1".
G
DTP/external interrupt enable register (ENIR)
This register enables or disables DTP/external interrupt requests from external peripheral devices.
I Details of Pins and Interrupt Numbers
Table 12.2-1 shows the pins and interrupt numbers used in the DTP/external interrupt.
Table 12.2-1 Pins and Interrupt Numbers Used by DTP/External Interrupt
332
Pin
P44/RX
P24/INT4
P25/INT5
P26/INT6
P27/INT7
Channel
RX
4
5
6
7
Interrupt Number
#15 (0F
)
H
#24 (18
)
H
#27 (1B
)
H
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