Software Interrupt - Fujitsu MB90895 Series Hardware Manual

16 bit, controller manual
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3.5.9

Software interrupt

The software interrupt is a function for transiting control from the current-executing
program to the interrupt processing program defined by user by execution of a software
interrupt instruction (INT instruction). The software interrupt is held during execution of
a software interrupt.
I Start and operation of software interrupt
G
Start of Software Interrupt
A software interrupt is started by executing the INT instruction. It does not have an interrupt request flag or
an interrupt enable flag. An interrupt request is generated immediately after the INT instruction is executed.
G
Hardware interrupt inhibition
Interrupts by the INT instruction have no interrupt level and the interrupt level mask register (ILM) is not
updated. During execution of the INT instruction, the interrupt enable flag (CCR: I) is set to "0" and a
hardware interrupt is masked.
When enabling a hardware interrupt during software interrupt processing, set the interrupt enable flag
(CCR: I) to "1" during software interrupt processing.
G
Operation of software interrupt
When the INT instruction is executed, the software interrupt processing microcode in the CPU is started.
The software interrupt processing microcode saves the values of the dedicated registers in the system stack;
branching to the address of the corresponding interrupt vector table after a hardware interrupt is masked
(CCR: I = 0).
I Return from Software Interrupt
When the interrupt return instruction (RETI) is executed in the interrupt processing program, the values of
the dedicated registers saved in the system stack are returned to each register and the operation is returned
to the processing performed before branching to interrupt processing.
Note:
When the program bank register (PCB) is "FF
overlaps the table for the INT #vct8 instruction. A CALLV and INT #vct8 instructions can
not use the same address in creating a program.
", the vector area for the CALLV instruction
H
CHAPTER 3 CPU
77

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