Fujitsu MB90895 Series Hardware Manual page 461

Table 15.3-4 Functions of Serial Status Register 1 (SSR1) (2/2)
bit name
bit14 ORE:
Overrun error flag bit
bit15 PE:
parity error flag bit
Function
Detect an overrun error in receiving.
• This bit is set to "1" when an overrun error occurs.
• This bit is cleared when "0" is written to the receive error flag
clear bit (SCR1 register bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
interrupt request is issued when an overrun error occurs.
• When the overrun error flag bit is set (bit 14: ORE = 1), data
in the serial input data register (SIDR1) is invalid.
Detect an overrun error in receiving.
• This bit is set to "1" when a parity error occurs.
• This bit is cleared when "0" is written to the receive error flag
clear bit (SCR1 register bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
interrupt request is issued when a parity error occurs.
• When the parity error flag bit is set (bit 15: PE = 1), data in
the serial input data register 1 (SIDR1) is invalid.
CHAPTER 15 UART1
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