Generation Of Transmit Interrupt And Timing Of Flag Set - Fujitsu MB90895 Series Hardware Manual

14.4.2

Generation of Transmit Interrupt and Timing of Flag Set

An interrupt during transmission is generated when serial output data register 0
(SODR0) becomes empty, or ready to accommodate the next data to transmit.
I Generation of Transmit Interrupt and Timing of Flag Set
G
Set and clear of transmit data empty flag bit
The transmit data write flag bit (SSR0: TDRE) is set when the transmit data written to serial output data
register 0 (SODR0) is transferred to the transmission shift register, making it ready to write the next data to
transmit.The transmit data write flag bit (SSR0: TDRE) is cleared to "0" when the next data to transmit is
written to serial output data register 0 (SODR0).
Transmission and timing of flag set are shown in Figure 14.4-2.
[Operating mode 0, 1]
SODR0 writing
SSR0: TDRE
SOT0 output
[Operating mode 2]
Transmission interrupt generating
SODR0 writing
SSR0: TDRE
SOT0 output
ST : Start bit
D0 to D7 : Data bit
SP : Stop bit
A/D : Address/data select bit
Figure 14.4-2 Transmission and Timing of Flag Set
Transmission interrupt generating
ST D0 D1 D2 D3
D0 D1 D2 D3 D4
Transmission interrupt generating
D7 SP
D5 D6 SP
D4
A/D
Transmission interrupt generating
D0 D1 D2
D6 D7
D5
CHAPTER 14 UART0
ST D0 D1 D2 D3
D6 D7
D3 D4 D5
403