Fujitsu MB90895 Series Hardware Manual page 137

G
Transition from sub clock mode to main clock mode
When the sub clock select bit (CKSCR: SCS) is rewritten from "0" to "1", the sub clock switches to the
main clock after the main clock oscillation stabilization wait time has elapsed.
Notes: • For switching from subclock mode to main clock mode using the external reset pin (RST
pin), input the Low level for at least oscillator's oscillation time* + 100 µs + 16 machine
cycles (main clock).
*:The oscillation time for the oscillator is the period of time taken until its amplitude reaches
90%.
It takes several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/
ceramic oscillators, and 0 ms for external clocks.
• There is no sub-clock in MB90F897S.
G
Transition from PLL clock mode to sub clock mode
When the sub clock select bit (CKSCR: SCS) is rewritten from "1" to "0", the PLL clock switches to the
sub clock.
G
Transition from sub clock mode to PLL clock mode
When the sub clock select bit (CKSCR: SCS) is rewritten from "0" to "1", the sub clock switches to the
PLL clock after the main clock oscillation stabilization wait time has elapsed.
I Selection of PLL Clock Multiplication Rate
The PLL clock multiplication rate can be set from x1 to x4 by writing values of 00
multiplication rate select bits (CKSCR: CS1, CS0).
I Machine clock
The PLL clock, main clock, and sub clock output from the PLL multiplying circuit are used as machine
clocks. These machine are clocks supplied to the CPU or peripherals.Any of the main clock, PLL clock,
and sub clock can be selected by writing to the sub clock select bit (CKSCR: SCS) and the PLL clock
select bit (CKSCR: MCS).
Notes: • The machine clock is not switched immediately even when the PLL clock select bit
(CKSCR: MCS) and subclock select bit (CKSCR: SCS) are updated. Before running a
peripheral resource that depends on the machine clock, switch the machine clock to a
desired clock, then reference the value of the PLL clock flag bit (CKSCR: MCM) or
subclock flag bit (CKSCR: SCM) to check that the machine clock has been switched to the
selected clock.
• When the PLL clock select bit (CKSCR: MCS) is "0" (PLL clock mode) and the subclock
select bit (CKSCR: SCS) is "0" (subclock mode), the SCS bit supersedes the MCS bit,
causing a transition to the subclock mode.
• While the clock mode is being switched, do not switch the CPU to any other clock mode
or to low power consumption mode until the current process of mode switching is
completed.Check the MCM and SCM bits in the clock select register (CKSCR) to make
sure that the transition to the new clock mode has been completed. If the mode is switched
to another clock mode or low power consumption mode before completion of switching,
the mode may not be switched.
• There is no sub-clock in MB90F897S.
CHAPTER 3 CPU
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