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16.3.16
Receive overrun register (ROVRR)
The reception overrun register (ROVRR) indicates that an overrun occurs (the
corresponding message buffer is in the receive complete state) at storing the received
message in the message buffer.
I Receive overrun register (ROVRR)
7
6
5
R/W
R/W
R/W
R/W
: Read/Write
: Reset value
Figure 16.3-24 Receive overrun register (ROVRR)
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
bit0
ROVR0
bit1
ROVR1
bit2
ROVR2
bit3
ROVR3
bit4
ROVR4
bit5
ROVR5
bit6
ROVR6
bit7
ROVR7
Reset value
0 0 0 0 0 0 0 0
B
Receive overrun bit 0 (Message buffer 0)
Not overrun error occurs
0
1
Overrun error occurs
Receive overrun bit 1(messag buffer1)
Not overrun error occurs
0
1
Overrun error occurs
Receive overrun bit 2 (messag buffer2)
Not overrun error occurs
0
1
Overrun error occurs
Receiv overrun bit 3 (messag buffer 3)
Not overrun error occurs
0
Overrun error occurs
1
Receiv overrun bit 4 (messag buffer 4)
Not overrun error occurs
0
1
Overrun error occurs
Receiv overrun bit 5 (messag buffer 5)
Not overrun error occrs
0
1
Overrun error occurs
Receiv overrun bit 6 (messag buffer 6)
Not overrun error occrs
0
1
Overrun error occrs
Receiv overrun bit 7 (messag buffer 7)
Not overrun error occrs
0
Overrun error occrs
1
CHAPTER 16 CAN controller
519
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