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CHAPTER 7 16-bit I/O timer
Table 7.3-2 Functions of Timer Counter Control Status Register (TCCS)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
230
bit name
CLK2, CLK1, CLK0:
These bits set the count clock to the 16-bit free-run time.
Count clock selection
Note:
bits
CLR:
This bit clears the count value of the 16-bit free-run timer.
Timer count clear bit
When set to "1": Clears timer counter data register (TCDT)
to "0000
When the bit is set to "0": No effect.
Read: "0" is always read.
•
•
Reserved: reserved bit
Always set this bit to "0".
STOP:
This bit enables or disables (stops) the count operation of the 16-
Timer count bit
bit free-run timer.
When set to "0": Enables count operation. The 16-bit timer
counter data register (TCDT) starts incrementing in
synchronization with the count clock selected by the count clock
select bits (CLK1 and CLK0).
When set to "1": Stops count operation
IVFE:
This bit enables or disables an interrupt request generated when
Overflow interrupt
the 16-bit free- run timer overflows.
enable bit
When set to "0": No interrupt request generated at overflow
(IVF = 1)
When set to "1": Generates interrupt request at overflow
(IVF = 1)
IVF:
This bit indicates that the 16-bit free-run timer has overflowed.
Overflow generation flag
•
bit
•
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
When EI
Read by read modify write instructions: "1" is always read.
Function]
1)Set the count clock after stopping the count operation
(STOP = 1).
2)When rewriting the count clock, write "1" to the timer
counter clear bit (CLR) and clear the count value.
"
H
When the count value changes, the CLR bit is cleared.
When clearing the count value while stopping the count
operation, write "0000
" to the timer counter data register
H
(TCDT).
This bit is set to "1" either when the 16-bit free-run timer
causes an overflow or when mode setting causes a compare
match with compare register 0 to clear the counter.
When an overflow occurs with an overflow interrupt enabled
(IVFE = 1), an interrupt request is generated.
2
OS started: Bit cleared
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