Fujitsu MB90895 Series Hardware Manual page 498

CHAPTER 16 CAN controller
G
Bit timing register (BTR)
This register sets the division ratio at which CAN bit timing is generated.
G
Control status register (CSR)
This register controls the operation of the CAN controller.It indicates the state of transmitting/receiving and
the CAN bus, controls interrupts, and controls the bus halt and indicates its state.
G
Receive/transmit error counter register (RTEC)
This register indicates the number of times transmit and receive errors have occurred.It counts up when an
error occurs in transmitting and receiving messages and counts down when transmitting and receiving are
performed normally.
G
Message buffer validating register (BVALR)
This register enables or disables a specified message buffer.It also indicates the enabled/disabled status.
G
IDE register (IDER)
This register sets the frame format of each message buffer.It sets the standard frame format or extended
frame format.
G
Transmit request register (TREQR)
This register sets a transmit request to each message buffer.
G
Transmit cancel register (TCANR)
This register cancels transmit requests held in each buffer message.
G
Transmit RTR register (TRTRR)
This register selects a frame format transmitted to each message buffer.It selects the data frame or remote
frame.
G
Remote frame receive waiting register (RFWTR)
This register sets the condition for transmitting start when a transmit request of the data frame is set.
G
Transmit complete register (TCR)
Sets the bit which is corresponds to the number of the message buffer that completes message transmitting.
G
Transmit complete interrupt enable register (TIER)
This register controls the generation of an interrupt request when each message buffer completes
transmitting.When an interrupt is enabled, an interrupt request is generated when transmitting is completed.
G
Receive complete register (RCR)
This register sets the bit corresponding to the number of the message buffer that completes receiving
message.
G
Receive complete interrupt enable register (RIER)
This register controls output of an interrupt request when each message buffer completes receiving.If
output of an interrupt request is enabled, an interrupt request is output at completion of receiving.
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