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G
Oscillation clock generator
This generator generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external
clock to the high-speed oscillation pins.
G
Sub clock generator
This generator generates a sub clock (SCLK) by connecting an oscillator or inputting an external clock to
the low-speed oscillation pins (X0A, X1A).
G
PLL multiplying circuit
This circuit multiplies the oscillation clock and supplies it as a PLL clock (PCLK) to the clock selector.
G
Clock selector
This selector selects the clock that is supplied to the CPU or resources from the main clock, sub clock, and
four types of PLL clock.
G
Clock select register (CKSCR)
This register is used to select between the oscillation clock and PLL clock, between the main clock and
subclock, the oscillation stabilization wait time, and the PLL clock multiplier.
G
Oscillation stabilization wait time selector
This selector selects the oscillation stabilization wait time of the oscillation clock.These bits are used to
select one from four timebase timer outputs.
Note:
There is no sub-clock in MB90F897S.
CHAPTER 3 CPU
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