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3.2.4.1
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register consisting of bits indicating the
result of instruction execution, and the bits enabling or disabling the interrupt request.
I Configuration of Condition Code Register (CCR)
Figure 3.2-11 "Configuration of Condition Code Register (CCR)" shows the configuration of the CCR
register.
Figure 3.2-11 Configuration of Condition Code Register (CCR)
bit15
PS
ILM2
0
-
: Unused
X
: Undefined
G
Interrupt enable flag (I)
All interrupts except software interrupts are enabled when the interrupt enable flag (CCR: I) is set to "1",
and are disabled when the interrupt enable flag is set to "0". This flag is cleared to "0" by a reset.
G
Stack flag (S)
This flag sets the pointer for stack processing.
When the stack flag (CCR: S) is "0", the user stack pointer (USP) is enabled. When the stack flag (CCR: S)
is "1", the system stack pointer (SSP) is enabled. If an interrupt is accepted or a reset occurs, the flag is set
to "1".
G
Sticky-bit flag (T)
This flag is set to "1" if any of the items of data shifted out by a carry is "1" when the logic right-shift
instruction or arithmetic right-shift instruction is executed. If all the shifted-out data is "0" or the shift
amount is "0", this flag is set to 0.
G
Negative flag (N)
If the most significant bit (MSB) of the operation result is "1", this flag is set to "1". If the MSB is "0", the
flag is cleared to "0".
RP
ILM
14
13 12 11 10
9
B4 B3 B2 B1 B0
ILM1 ILM0
0
0
0
0
0
0
Interrupt enable flag
Stack flag
Sticky bit flag
Negative flag
0 flag
Overflow flag
Carry flag
CCR
8
7
6
5
4
3
I
S
T
N
-
0
-
0
1
X
X
CHAPTER 3 CPU
2
1
bit0
CCR reset value
Z
V
C
- 0 1 X X X X X
X
X
X
B
41
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