Fujitsu MB90895 Series Hardware Manual page 203

I Block Diagram of Pins of Port 5
PDR (Port data register)
PDR read
PDR write
DDR (Port direction register)
DDR write
DDR read
Standby control Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
I Registers for Port 5
• The registers for port 5 are PDR5, DDR5, and ADER.
• The ADER sets input of an analog signal to the analog input pin to enabled or disabled.
• The bits composing each register correspond to the pins of port 5 one-to-one.
Table 4.7-2 shows correspondence between registers and pins for port 5.
Table 4.7-2 Correspondence between Registers and Pins for Port 5
Port Name
PDR5 to DDR5
Port 5 ADER
Corresponding pin
Figure 4.7-1 Block Diagram of Pins of Port 5
ADER
Output latch
Direction latch
Bits of Related Registers and Corresponding Pins
bit7 bit6
ADE7 ADE6
P57 P56
Analog input
bit5 bit4 bit3
ADE5 ADE4 ADE3
P55 P54 P53
CHAPTER 4 I/O PORT
Pch
Pin
Nch
Standby control (SPL=1)
bit2 bit1 bit0
ADE2 ADE1 ADE0
P52 P51 P50
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