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I Function of Interrupt Control Register
G
Interrupt level setting bits (IL2 to IL0)
Sets corresponding peripheral Functions of Interrupt Control Register. At reset, the bits are set to level 7
(IL2 to IL0 = "111
Table 3.5-4 shows the relationship between the interrupt level setting bits and interrupt levels.
Table 3.5-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels
IL2
0
0
0
0
1
1
1
1
G
Extended Intelligent I/O Service (EI
When an interrupt occurs with the ISE bit set to "1", the EI
ISE bit set to "0", ordinary interrupt processing is started. If the EI
status bits S1 and S0 are not "00
2
EI
OS function, this bit must be set to "0" by the program. At reset, the ISE bit is set to "0".
G
2
EI
OS channel select bits (ICS3 to ICS0)
These bits select EI
the ICS3 to ICS0 bits. At reset, the ICS3 to ICS0 are set to" 0000
Table 3.5-5 shows the correspondence between the EI
Table 3.5-5 Correspondence between EI
Addresses (1/2)
ICS3
0
0
0
0
0
": no interrupt).
B
IL1
IL0
0
0
1
1
0
0
1
1
2
OS) enable bit (ISE)
"), the ISE bit is cleared. When the corresponding resources have no
B
2
OS channels. The EI
ICS2
ICS1
ICS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
0
0(maximum interrupt)
1
0
1
0
1
0
6 (lowest interrupt)
1
2
OS is started. When an interrupt occurs with the
2
OS descriptor addresses are set according to the setting values of
2
OS channel select bits and descriptor addresses.
2
OS Channel Select Bits and Descriptor
Channel to be Selected
0
1
2
3
4
CHAPTER 3 CPU
Interrupt Level
↑
↓
7 (No interrupt)
2
OS end condition is satisfied (when the
".
B
Descriptor Address
000100
H
000108
H
000110
H
000118
H
000120
H
67
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