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CHAPTER 14 UART0
G
Reception Interrupt
When a receive interrupt is enabled (SSR0: RIE = 1), a receive interrupt request is issued at completion of
data receiving (SSR0: RDRF = 1) or when any one of the overrun error (SSR0: ORE = 1), framing error
(SSR0: FRE = 1), and parity error (SSR0: PE = 1) occurs.
When serial input data register 0 (SIDR0) is read, the receive data load flag (SSR0: RDRF) is automatically
cleared to 0.Each reception error flag (SSR0: PE, ORE, FRE) is cleared to "0" when "0" is written to the
reception error flag clear bit (SCR0: REC).
Note:
If a reception error (parity error, overrun error, or framing error) occurs, correct the error as
necessary, and then write "0" to the reception error flag clear bit (SCR0: REC) to clear each
reception error flag.
G
Transmission Interrupt
The transmit data write flag bit (SSR0: TDRE) is set to "1" when data to transmit is transferred from serial
output data register 0 (SODR0) to the transmission shift register.
If the transmission interrupt enable bit (SSR0: TIE) contains 1, a transmission interrupt request is
generated.
I Interrupt Related to UART0 and EI
Note:
For details of the interrupt number, interrupt control register, and interrupt vector address, see
3.5 Interrupt.
2
I EI
OS Function of UART0
The UART0 supports EI
transmit interrupts.
G
At reception:
MB90895 series cannot use interrupt vectors as it contains no I
G
At transmission:
Since the interrupt control register (ICR14) is shared with the UART0 for reception interrupts, EI
be started only when no interrupt is used for transmission by the UART0.
400
2
OS
2
2
OS.Consequently, EI
OS can be started separately for receive interrupts and
2
C interface.
2
OS can
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