Fujitsu MB90895 Series Hardware Manual page 181

I Block Diagram of Port-1 Pins (in Single Chip Mode)
Port data register (PDR)
PDR read
PDR write
Port direction register (DDR)
DDR write
DDR read
Standby control Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
I Block Diagram of Port 1 Pins
• Registers for Port 1 (in Single Chip Mode)
• The bits composing each register correspond to the pins of port 1 one-to-one.
Table 4.3-2 shows the correspondence between the registers and pins of port 1.
Table 4.3-2 The correspondence between the registers and pins of port 1
Port Name
port 1
Figure 4.3-1 Block Diagram of Pins of Port 1
Resource input
Output latch
Direction latch
Bits of Related Registers and Corresponding Pins
PDR1, DDR1 bit7
Corresponding pin P17
Resource output
Resource output
acceptance
Standby control (SPL=1)
bit6 bit5 bit4 bit3
P16 P15 P14 P13
CHAPTER 4 I/O PORT
Pch
Pin
Nch
bit2 bit1 bit0
P12 P11 P10
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