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G
Reception Interrupt
When a receive interrupt is enabled (SSR1 register bit 9: RIE = 1), a receive interrupt request is issued at
completion of data receiving (SSR1 register bit 12: RDRF = 1) or when any one of the overrun error (SSR1
register bit 14: ORE = 1), framing error (SSR 1 register bit 13: FRE = 1), and parity error (SSR 1 register
bit 15: PE = 1) occurs.
The receive data load flag (SSR1 register bit 12: RDRF) is cleared to 0 automatically when the serial input
data register 1 (SIDR1) is read.Each receive error flag (SSR1 register bit 15, 14, 13: PE, ORE, FRE) is
cleared to "0" when "0" is written to the receive error flag clear bit (SCR1 register bit 10: REC).
Note:
If a receive error (parity error, overrun error, framing error) occurs, correct the error as
necessary, and then write "0" to the receive error flag clear bit (SCR1 register bit 10: REC) to
clear each receive error flag.
G
Transmission Interrupt
When send data is transmitted from the serial output data register 1 (SODR1) to the transmit shift register,
the transmit data write flag bit (SSR1 register bit 11: TDRE) is set to "1".
When a transmit interrupt is enabled (SSR1 register bit 8: TIE = 1), a send interrupt request is issued.
I Interrupt Related to UART1 and EI
Reference:
For details of the interrupt number, interrupt control register, and interrupt vector address, see
Interrupt.
2
I EI
OS Function of UART1
The UART1 supports EI
transmit interrupts.
G
At reception:
2
EI
OS can be used regardless of the states of other resources.
G
At transmission:
Since the interrupt control registers (ICR13, 14) are shared with receive interrupts of UART1, EI
be started only when UART1 transmit interrupts are not used.
2
OS
2
2
OS.Consequently, EI
OS can be started separately for receive interrupts and
CHAPTER 15 UART1
2
OS can
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