Table 7-22: Single Color 8-Bit Panel A.c. Timing (Format 1); Figure 7-26: Single Color 8-Bit Panel A.c. Timing (Format 1) - Epson S1D13504 Technical Manual

Page 72
Sync Timing
Data Timing
Symbol
t1
FPFRAME setup to FPLINE falling edge
t2
FPFRAME hold from FPLINE falling edge
t3
FPLINE pulse width
t4
FPLINE period
t5a
FPSHIFT2 falling edge to FPLINE rising edge
t5b
FPSHIFT falling edge to FPLINE rising edge
t6
FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge
t7
FPSHIFT2, FPSHIFT period
t8a
FPSHIFT falling edge to FPLINE falling edge
t8b
FPSHIFT2 falling edge to FPLINE falling edge
t9
FPLINE falling edge to FPSHIFT rising edge
t10
FPSHIFT2, FPSHIFT pulse width high
t11
FPSHIFT2, FPSHIFT pulse width low
t12
UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
t13
UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1 = t4 - 9Ts
min min
3. t4 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
min
4. t5 = [((REG[05h] bits [4:0]) + 1)*8 - 27]+T11 Ts
min
5. t5 = [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
min
6. t8 = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
min
7. t8 = [((REG[05h] bits [4:0]) + 1)*8 - 18]+T11 Ts
min
S1D13504
X19A-A-002-18
FPFRAME
FPLINE
FPLINE
t5a
FPSHIFT
FPSHIFT2
UD[3:0]
LD[3:0]

Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1)

Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1)

Parameter
t1
t2
t3
t5b
t6
t9
t8a
t8b
t12
note 2
note 3
note 4
note 5
t14 + 2
note 6
note 7
Epson Research and Development
Vancouver Design Center
t4
t7
t10 t11
t13
1 2
Min Typ Max
9
9
4
18
2
2
1
1
Hardware Functional Specification
Issue Date: 01/01/30
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts