Register/Bit Table - Epson S1R75801F00A Technical Manual

S1R72803F00A

8.1.2 Register/Bit Table

The base address of this register is 0x100000.
Address Register Name
0x00 MainIntStat
0x01 SubIntStat
0x02 (Reserved)
0x03 DmaIntStat
0x04 LinkIntStat1
0x05 LinkIntStat0
0x06 PhyIntStat
0x07 (Reserved)
0x08 MainIntEnb
0x09 SubIntEnb
0x0A (Reserved)
0x0B DmaIntEnb
0x0C LinkIntEnb1
0x0D UltraDmaMode
0x0E PhyIntEnb
0x0F (Reserved)
0x10 ChipCtl
0x11 HW_Revision
0x12 ApetusTestOutPut_H
0x13 ApetusTestOutPut_L
0x14 LCTestIndex
0x15 LCTestWindow
0x16 SBP2TestIndex
0x17 SBP2TestWindow
0x18 LinkCtl_H
0x19 LinkCtl_L
0x1A LinkStat
0x1B PriReqCnt
0x1C RetryLimit_H
0x1D RetryLimit_L
0x1E MaxRetry
0x1F IRM_Stat
0x20 NODE_IDS_H
0x21 NODE_IDS_L
0x22 (Reserved)
0x23 (Reserved)
0x24 PhyAccCtl_H
0x25 PhyAccCtl_L
0x26 PhyRdstat_H
0x27 PhyRdstat_L
0x28 ChnlIndex
0x29 ChnlWindow
0x2A CmprIndex
0x2B CmprWindow
0x2C CYCLE_TIME_H
0x2D CYCLE_TIME_MH
0x2E CYCLE_TIME_ML
0x2F CYCLE_TIME_L
22
bit7 bit6
SubIntStat TxIsoCmp RxDmaCmp
SelfIDdone SelfIDerr HwSBP2Err HwSBP2BRs LinkIntStat1
TxAsyRtyGo TxAsyBCSent RxDmaFaild
UnExpCh DupliCh IsoArbFaild
SubGap ArbGap
EnSubIntStat EnTxIsoCmp EnRxDmaCmp EnTxAsyCmp EnHwSBP2Cm EnIDE_DmaC EnIDE_INTRQ EnBusReset
EnSelfIDdone EnSelfIDerr EnHwSBP2Err EnHwSBP2BRst EnLinkIntStat1 EnLinkIntStat0 EnPhyIntStat EnDmaIntStat
EnTxAsyRtyGo EnTxAsyBCSe EnRxDmaFaild EnTxAsyFaild EnTxIsoFaild EnTxAsyBRAb EnTxAsyMiss
EnUnExpCh EnDupliCh EnIsoArbFaild EnCycTooLon EnCycOverFlw EnCycEvent
EnSubGap EnArbGap
Suspend
PassSelfID PassPhyPkt PassBrPkt
EnLink PLIFrst
SecLimit[2:0]
NoIRM WonIRM
BusID[1:0]
RdReq WrReq
Cycle Count[3:0]
bit5 bit4 bit3
TxAsyCmp HwSBP2Cmp IDE_DmaCm IDE_INTRQ
TxAsyFaild
RxOnTardy
CycTooLong CycOverFlw
EnRxOnTardy EnRxHcrcErr EnRxUnkTcod EnTxRtyExced
HW_Revision[7:0]
Chip Test Register
EnPosWB EnPosWQ
IgnrBChdr IgnrBCdata
Priority Budget Request Count [5:0]
CycLimit[7:0]
BusID[9:2]
Physical ID[5:0]
Write Data[7:0]
Read Data[7:0]
Channel Window
Compare Address Window
Cycle Second[6:0]
Cycle Count[11:4]
Cycle Offset[7:0]
EPSON
bit2 bit1
LinkIntStat0 PhyIntStat
TxIsoFaild TxAsyBRAbort TxAsyMiss
RxHcrcErr RxUnkTcode
CycEvent CycLost
Phy_int PhyWrDone
EnCycLost
EnPhy_int EnPhyWrDone EnPhyRdDone
IDE_MdlRst SendTardy
APHY EnAcc
RxBusyMode DualRtyEnb
ID_Valid Root
CycLimit[12:8]
MaxRetry[3:0]
IRM_ID[5:0]
Request Address[3:0]
Read Address[3:0]
Channel Index
Compare Address Index
Cycle Offset[11:8]
bit0
BusReset
DmaIntStat
TxRtyExced
CycArbFail
PhyRdDone
EnCycArbFail
SoftReset
Cmstr
SinglRtyEnb
CablPwSts
CycCnt[12]