Table 7-22: Single Color 8-Bit Panel A.c. Timing (Format 1); Figure 7-26: Single Color 8-Bit Panel A.c. Timing (Format 1); Vancouver Design Center - Epson S1D13504 Technical Manual

Color graphics lcd/crt controller

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FPFRAME setup to FPLINE falling edge

FPFRAME hold from FPLINE falling edge

FPLINE pulse width

FPLINE period

FPSHIFT2 falling edge to FPLINE rising edge

FPSHIFT falling edge to FPLINE rising edge

FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge

FPSHIFT2, FPSHIFT period

FPSHIFT falling edge to FPLINE falling edge

FPSHIFT2 falling edge to FPLINE falling edge

FPLINE falling edge to FPSHIFT rising edge

FPSHIFT2, FPSHIFT pulse width high

FPSHIFT2, FPSHIFT pulse width low

UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge

UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 27]+T11 Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 18]+T11 Ts

Hardware Functional Specification

Issue Date: 01/11/06

Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1)

X19A-A-002-19

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