SED1225 Series
SIGNAL TIMING CHARACTERISTICS
(1) MPU bus write timing (80 series)
A0
XCS
t
AW8
XWR
D0 to D7
Item
Address setup time
Address hold time
XCS setup time
System cycle time
Write "Lo" pulse width (XWR)
Write "Hi" pulse width (XWR)
Data setup time
Data hold time
Item
Address setup time
Address hold time
XCS setup time
System cycle time
Write "Lo" pulse width (XWR)
Write "Hi" pulse width (XWR)
Data setup time
Data hold time
*1 The input signal rise and fall times (
t
*2 "
" is defined by the overlap time of XCS low level and XWR low level.
CCL
3–28
t
AC8
t
CCL
t
DS8
Signal
Symbol
A0
XCS
XWR
D0 to D7
Signal
Symbol
A0
XCS
XWR
D0 to D7
t
t
r,
f) are defined to be 25 nsec max (except for RES input).
t
r
t
AH8
t
CYC8
t
t
DH8
(Ta = –30 to +85°C, V
Conditions
t
AW8
t
AH8
t
AC8
t
CYC8
All timing must be based on
t
CCL
20% and 80% of V
SS
t
CCH
t
DS8
t
DH8
(Ta = –30 to +85°C, V
Conditions
t
AW8
t
AH8
t
AC8
t
CYC8
All timing must be based on
t
CCL
20% and 80% of V
SS
t
CCH
t
DS8
t
DH8
V
x 0.8 [V]
SS
V
x 0.2 [V]
SS
EPSON
CCH
= –3.6V to –1.7V)
SS
Min.
Max.
60
—
30
—
0
—
1850
—
150
—
.
1650
—
50
—
50
—
= –3.3V to –2.7V)
SS
Min.
Max.
60
—
30
—
0
—
1150
—
100
—
.
1000
—
20
—
20
—
t
f
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns