Direct Connection To The Toshiba Tx3912; Hardware Description - Epson S1D13504 Technical Manual

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4 Direct Connection to the Toshiba TX3912

When connecting the S1D13504 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of TX3912 to S1D13504 Direct Connection

Interfacing to the Toshiba MIPS TX3912 Processor

Issue Date: 01/10/26

The S1D13504 is easily interfaced to the Toshiba TX3912 processor. In the direct

connection implementation, the S1D13504 occupies PC Card slot #1 of the TX3912.

Although the address bus of the TX3912 is multiplexed, it can be demultiplexed using an

advanced CMOS latch (e.g., 74ACT373). The direct connection implementation makes use

of the Generic MPU host bus interface capability of the S1D13504.

The following diagram demonstrates a typical implementation of the TX3912 to S1D13504

Clock divider

For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".

System RESET

X19A-G-012-05

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