Clock Configuration Register; Table 8-8: Pixel Panning Selection; Table 8-9: Pclk Divide Selection; Vancouver Design Center - Epson S1D13504 Technical Manual

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Pixel Panning Register
REG[18h]
Screen 2 Screen 2
Pixel Panning Pixel Panning
Bit 3 Bit 2
Number of Bits-Per-Pixel
bits 7-4
bits 3-0

8.2.5 Clock Configuration Register

Clock Configuration Register
REG[19h]
n/a n/a
bit 2
bits 1-0
PCLK Divide Select Bits [1:0]
Hardware Functional Specification
Issue Date: 01/01/30
Screen 2 Screen 2
Pixel Panning Pixel Panning
Bit 1 Bit 0
This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each screen
can be independently panned to the left by programming its respective Pixel Panning Bits to a non-
zero value. This value represents the number of pixels panned. The maximum pan value is dependent
on the display mode as shown in the table below.

Table 8-8: Pixel Panning Selection

1
2
4
8
15/16
Smooth horizontal panning can be achieved by a combination of this register and the Display Start
Address register. See Section 10, "Display Configuration" on page 116 and S1D13504
Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details.
Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
n/a n/a
MCLK Divide Select
When this bit = 1 the memory clock (MCLK) frequency is half of the input clock frequency. When
this bit = 0 the memory clock frequency is equal to the input clock frequency.
PCLK Divide Select Bits [1:0]
These bits determine the amount of divide from the memory clock to generate the pixel clock (PCLK):

Table 8-9: PCLK Divide Selection

00
01
10
11
See Section 11.2, "Frame Rate Calculation" on page 120 for selection of PCLK frequency.
b
Screen 1 Screen 1
Pixel Panning Pixel Panning
Bit 3 Bit 2
Screen 2 Pixel Panning Bits Used
Bits [3:0]
Bits [2:0]
Bits [1:0]
Bit 0
---
MCLK Divide
n/a
Select
MCLK/PCLK Frequency Ratio
1
2
3
4
Page 101
RW
Screen 1 Screen 1
Pixel Panning Pixel Panning
Bit 1 Bit 0
RW
PCLK Divide PCLK Divide
Select Bit 1 Select Bit 0
S1D13504
X19A-A-002-18