Sdram Timing For Write Access - Siemens ERTEC 200P-2 Manual

3.3.1.3.2 SDRAM Timing for write access

Note: The Bank signals BA0, BA1 are part of the address bus A. They are given here
separately for a better understanding.
Parame- Description
ter
t Clock Period
CK
t Clock Low Time
CL
t Clock High Time
CH
t Command
CMS
Time
t Command Hold Time
CMH
t Address Setup Time
AS
t Address Hold Time
AH
t Data Setup Time
DS
t Data Hold Time
DH
t RAS to CAS delay
RCD
t Row Address Strobe
RAS
t ROW cycle Time
RC
t Write to
WR
Time
t Row precharge
RP
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Min
7.8 ns
3.8 ns
3.8 ns
Setup 3.5 ns
1.4 ns
3.5 ns
1.4 ns
3.5 ns
1.4 ns
16 ns
t + t
RCD WR
t + t
RCD WR
t
RP
Precharge 16 ns
la- 24 ns
Max depends on Register
8.2 ns
4.2 ns
4.2 ns
6.6 ns
4.5 ns
6.6
4.5 ns
6.6 ns
4.5 ns
40 ns EXTENDED_CONFIG.TRC
D + 1
1)
+ -
1)
24 ns
458
No-
te
-
-
-
-
-
-
-
-
-
-
-
-
ERTEC 200P-2 Manual
Version 1.0