Secondary Boot Loader; Memory Swapping By The Secondary Boot Loader; Amba (Internal Bus System); Characteristics Of The Bus System In Ertec 200P - Siemens ERTEC 200P-2 Manual

2.3.1.6 Secondary Boot Loader

After leaving the boot ROM (processing of the primary boot loader), the ERTEC 200P is
configured as follows:
1. ARM mode is SYS
2. MMU is not changed; reset value.
3. Watchdog is set to 251 ms and active.
4. SDRAM is not initialized.
5. Stack pointer (SP) points to 0x0800_fd00.
6. 64k I-TCM from address 0x0000_0000 and 192k D-TCM
(TCM926_MAP.PARTITION_TCM926 = "001", not with NOR flash boot)
7. Shift mode active at EMC interface (EXTENDED_CONFIG.ASYNC_ADDR_MODE
= 1)

2.3.1.6.1 Memory Swapping by the Secondary Boot Loader

As the size of the I/D-TCM can be set variably in the ARM926, it is left to the secondary
boot loader to make the best settings for its needs.
The reset vector of the ARM926 processor points to address 0x0000_0000. That is why
the boot ROM starts at address 0x0000_0000 after reset (power on, HW, SW or watch-
dog reset). The boot ROM can also be addressed in its mirrored area (0x4000_8000)
It is left to the secondary boot loader to change the TCM mapping. To allow the second-
ary boot loader to be run, the primary boot loader switches the first page (64 KByte) of
the D-TCM to I-TCM (TCM926_MAP, see 2.3.10.9.14). If additional I-TCM is required, the
secondary boot loader must switch again.
Swapping is done by programming the MEM_SWAP.SWAP register (see 2.3.10.9.7).
This procedure ensures that the exception vectors are always assigned and prevents a
deadlock.

2.3.2 AMBA (Internal Bus System)

The ERTEC 200P has 2 internal bus systems. One is a high-performance communication
bus (multi-layer AHB) and one is a peripheral bus (APB).
All 6 masters (ARM926-I, ARM926-D, PN-IP-M1, PN-IP-M2, , GDMA controller and host
interface) and the slaves (D-TCM926, interrupt controller (ARM-ICU),
ter/memory, external memory controller (EMC), APB bridge, , peripheral interface (2
connections), PN-IP) are connected at the multi-layer AHB, which has a high data trans-
fer rate and high bus availability.
Over an AHB/APB bridge, the masters can access the rest of the peripherals which are
connected at the low-performance peripheral bus (APB). The AHB/APB bridge is the only
master at the peripheral bus.

2.3.2.1 Characteristics of the Bus System in ERTEC 200P

The table below sets out the characteristics of the internal bus system:
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Technical data subject to change
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GDMA regis-
ERTEC 200P-2 Manual
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