Siemens ERTEC 200P-2 Manual page 380

Enhanced real-time ethernet controller
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1
SW_RES
2
PWRON_HW_RES
3
SW_RES_ARM926
Register:
Bits:
Description:
Bit
Identifier
0
LOCK
1
LOSS
31dt2 reserved
Register:
Bits:
Description:
Bit
Identifier
31dt0 QVZ_AHB_ADR
Register:
Bits:
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
xh
1h
xh
PLL_STAT_REG
31dt0
Reset value: 1h
Status register for ERTEC 200P PLL
Reset
1h
0h
0h
QVZ_AHB_ADR
31dt0
Reset value: 0h
Address of incorrect addressing at the multi-layer AHB
Reset
00000000
h
QVZ_AHB_CTRL
31dt0
Reset value: 0h
380
h
ARM926 watchdog
r
1: The last reset was a software reset
h
r
1: The last reset was a power on or
h
hardware reset
r
1: The last reset was an ARM926
h
core software reset
Address: 18h
Attribu-
tes:
Attr. Function / Description
Lock: Lock at operating frequency
status of PLL:
0: PLL is unlocked
r
1: PLL is locked
h
This bit represents the current lock
status of the PLL.
Read-only
Loss: PLL input clock monitoring
status
1: PLL input clock not recognized
r
0: PLL input clock
h
This bit shows the current monitoring
status of the PLL input clock.
Read-only
Address: 1Ch
Attribu-
tes:
Attr. Function / Description
r
Address of incorrect addressing at the
h
multi-layer AHB
Address: 20h
Attribu-
tes:
rh
rh
rh
ERTEC 200P-2 Manual
Version 1.0

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