Siemens ERTEC 200P-2 Manual page 9

2.3.10.5 UART1...4 .....................................................................................................................305
2.3.10.5.1 UART Baud Rates......................................................................................................306
2.3.10.5.2 Address Mapping .......................................................................................................308
2.3.10.5.3 Register Description ...................................................................................................310
2.3.10.6 I²C .................................................................................................................................325
2.3.10.6.1 Baudrate generator ....................................................................................................325
2.3.10.6.2 IO Expansion Unit ......................................................................................................325
2.3.10.6.3 Important Software rules ............................................................................................326
2.3.10.6.4 Address Mapping .......................................................................................................328
2.3.10.6.5 Register Description ...................................................................................................329
2.3.10.7 SPI1/2 (Serial Peripheral Interface) ................................................................................335
2.3.10.7.1 Features of the SPI Interface ......................................................................................337
2.3.10.7.2 SSPMS IP Extension..................................................................................................338
2.3.10.7.3 SSPMS IP Integration ................................................................................................339
2.3.10.7.4 Send Support with Pause between Individual Characters ...........................................342
2.3.10.7.5 SPI Flash Boot ...........................................................................................................343
2.3.10.7.6 Address Mapping .......................................................................................................345
2.3.10.7.7 Register Description ...................................................................................................345
2.3.10.8 GPIO (General Purpose Input / Output) ..........................................................................348
2.3.10.8.1 GPIO Module Function Description ............................................................................349
2.3.10.8.2 Integration of the GPIO Module ..................................................................................352
2.3.10.8.3 GPIO Pad Multiplexing ...............................................................................................353
2.3.10.8.4 GPIO Assignment ......................................................................................................353
2.3.10.8.5 Address Mapping .......................................................................................................356
2.3.10.8.6 Register Description ...................................................................................................357
2.3.10.9 SCRB (System Control Register Block) ..........................................................................365
2.3.10.9.1 Hardware Identifier Register .......................................................................................365
2.3.10.9.2 Boot Register .............................................................................................................366
2.3.10.9.3 Config Register ..........................................................................................................366
2.3.10.9.4 Reset Registers .........................................................................................................367
2.3.10.9.5 ACCESS_ERROR and QVZ Register .........................................................................368
2.3.10.9.6 PLL Status Register ...................................................................................................368
2.3.10.9.7 Memory Swapping .....................................................................................................368
2.3.10.9.8 ARM Control Register ................................................................................................369
2.3.10.9.9 PHY Register .............................................................................................................369
2.3.10.9.10 AHB Burst Breaker Register .....................................................................................369
2.3.10.9.11 GPIO Control Register .............................................................................................369
2.3.10.9.12 I²C Clock Divider ......................................................................................................370
2.3.10.9.13 EDC Register ...........................................................................................................370
2.3.10.9.14 ARM926 Mapping ....................................................................................................370
2.3.10.9.15 PAD Control Register ...............................................................................................370
2.3.10.9.16 Clear DMA Request .................................................................................................373
2.3.10.9.17 SPI Parity Error ........................................................................................................373
2.3.10.9.18 XHIF Mode ...............................................................................................................373
2.3.10.9.19 Ext. Driver Enable ....................................................................................................373
2.3.10.9.20 SPI Mode .................................................................................................................373
2.3.10.9.21 SD Signal Handling ..................................................................................................373
2.3.10.9.22 Address Mapping .....................................................................................................374
2.3.10.9.23 Register Description .................................................................................................376
2.4 Memory Mapping .........................................................................................................................415
2.4.1 Memory Mapping ARM926-I ..................................................................................................415
2.4.2 ARM926-D Memory Mapping .................................................................................................416
2.4.3 PN-IP Memory Mapping .........................................................................................................417
2.4.4 Host IF Memory Mapping .......................................................................................................418
2.4.5 GDMA Memory Mapping ........................................................................................................421
2.5 Detailed Address Mapping ..........................................................................................................422
2.6 Register Description ...................................................................................................................425
3 IO INTERFACE ......................................................................................................... 426
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Technical data subject to change
9 ERTEC 200P-2 Manual
Version 1.0