Wiring Of Pins Not Used; Figure 57: Sd Level Translation Circuit - Siemens ERTEC 200P-2 Manual

The following level translation circuit is recommended by using of GPIOs (see chapter
2.3.10.9.21). Comparator should be placed near transceiver. The 3,3V supply voltage
tolerance for POF transceiver is limited to +- 5%.

4.7 Wiring of pins not used

The following applies in general:
IN and INOUT pins that do not have an internal pull resistor must be connected to
an external pull resistor.
If the internal pull-up/pull-down resistor of the GPIOs is deactivated, it must be ac-
tivated with the SW or an external pull-up/pull-down resistor is to be connected.
For wiring PHY pins that are not used, see xxx
Signal Signal description
ATP Analog Test Function
TEST IC-Test-Mode
TMC1 Testmode_1
TMC2 Testmode_2
TACT TESTACT-TAP-RESET
TAP_SEL TAP Select
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change

Figure 57: SD level translation circuit

Dir
out Analog Test
Enable to monitor or drive specific nodes in the
analog circuit during analog test. For debugging
purposes it is recommended to have this pin ac-
cessable for an oscilloscope on a PCB. This pin is
not used in normal operation.
in IC Test Mode
Select signal for ASIC test.
For normal operation this pin must be connected by a
1k Ohm Pull down resistor to GND.
in Test Mode Control
Signal for ASIC test.
For normal operation this pin must be connected
directly to GND.
in Test Mode Control
Signal for ASIC test.
For normal operation this pin must be connected
directly to GND.
in Special Test Mode TAP Controller
Used for Boundary scan test.
For normal operation this pin must be connected by a
1k Ohm Pull down resistor to GND.
in TAP Select
486
Function description Ball
K18
R9
F12
R14
R12
T7
ERTEC 200P-2 Manual
Version 1.0