Arm926 Watchdog; Overview; Block Diagram; Figure 34: Block Diagram Arm926 Watchdog - Siemens ERTEC 200P-2 Manual

2.3.10.2
2.3.10.2.1

Overview

The ARM926 watchdog primarily consists of two counters with different widths (32 and 36
bit) that count down from a parameterized initial value.
The watchdog has the following principal characteristics:
The clock pulse supply is 125 MHz (APB clock)
One output signal of the Counter0 watchdog (XWD_OUT0) is output at an alter-
nate Function of a GPIO pin.
After the watchdog Counter0 expires an interrupt (WD_INT: WD_INT_ARM926) is
generated (IRQ27, see chapter 2.3.2.14).
After the watchdog Counter1 expires (XWD_OUT1) the 'XRES_ARM926_WD' is
generated (see chapter 2.3.9.4.4).

Block diagram

2.3.10.2.2
APB-Bus
XRES_WD
CLK_WD
Counter0:
Counter0 is a 32-bit wide counter output that counts to 0 starting with the value passed in
the RELD0(_LOW/_HIGH) register with the clock pulse from the CLK_WD pin. The
watchdog is (re)started with Run/xStop_Z0=1 and, when required, stopped with
Run/xStop_Z0=0.
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change

ARM926 Watchdog

Watchdog
WD_
CTRL/Status
Run/xStop_Z0
Status_Counter0
Load
Run/xStop_Z1
Status_Counter1
RELD0
(Low &
WDOG0
RELD1
(Low &
WDOG1
APB bus XRES
interface
CLK
(slave)

Figure 34: Block diagram ARM926 Watchdog

260
Counter0
(32-bit)
Run/xStop_Z0
Status_Counter0
Load
3
RELD0(31:0)
WDOG0(31:0)
3
Counter1
(36-bit)
Run/xStop_Z1
Status_Counter1
CLK
Load
3
RELD1(35:4)
RELD1(3:0)
3
WDOG1(35:4)
WD_IN
XWD_OUT0
XWD_OUT1
ERTEC 200P-2 Manual
Version 1.0