Siemens ERTEC 200P-2 Manual page 191

27dt8 <reserved>
29dt28 APB_SIZE
30 APB_RD_WR
31 ERROR_LOCK
Register: XHIF_CONTROL
Bits: 3dt0
Description:
Bit Identifier
0 XHIF_ACC_MODE
1 XHIF_POL_RDY
3dt2 XHIF_CPU_WIDTH
Register: XHIF_0_P0_RG
Bits: 31dt0
Description:
Bit Identifier
7dt0 XHIF_0_P0_RG_ROSL2
21dt8 XHIF_0_P0_RG_RW
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
00000h r
2h r
0h r
0h r
Reset value:
XHIF Interface Settings
After reset
and when the SCRB CONFIG_REG register is written, these
settings
are taken from the register
Reset Attr.
0h rh
0h rh
0h rh
Reset value:
Range value of the page #0
Reset Attr.
00h r
0000h r
191
The higher-value APB address
bits(31:8) are mirrored in the HostIF
"10": Word access (32-bit) ?? fixed
value as only word access possible
'0': RD access
'1': WR access
Set to '1' by the HW if erroneous
APB access is
detected. Further HW entries are
w
then blocked.
The SW must reset the bit to '0' to
enable
new entries.
Address:
0h Attributes:
Function / Description
w XHIF Handshake protocol: 0 =Intel
Mode, 1 =Motorola Mode
w '0': XHIF_XRDY is low_aktiv
'1': XHIF_XRDY is high_aktiv
Data bus width:
00 =8b *,
01 =16b,
w
10 =32b,
11 =32b
* 00 =8b is however not supported
by the XHIF interface.
Address:
0h Attributes:
Function / Description
Read only value = 0
w Read/Write part of the Range regis-
ter
70h
rh w
80h
r (w)
ERTEC 200P-2 Manual
Version 1.0