7.3.2
LBU Write to ERTEC 400 with separate Read/Write line (LBU_RDY_N active low)
LBU_CS_R_N/
LBU_CD_M_N
LBU_WR_N
LBU_A(20:0)/
LBU_SEG(1:0)
LBU_BE(1:0)_N
LBU_RDY_N
LBU_D(15:0)
Figure 13: LBU-Write-Sequence with separate RD/WR line
Parameter
t
chip select asserted to write pulse asserted delay
CSWS
t
address valid to write pulse asserted setup time
AWS
t
write pulse asserted to ready enabled delay
WRE
t
write pulse asserted to data valid delay
WDV
t
ready active pulse width
RAP
t
write pulse deasserted to chip select deasserted delay
WCSH
t
address valid to write pulse deasserted hold time
WAH
t
ready asserted to write pulse deasserted delay
RTW
t
data valid/enabled to read pulse deasserted hold time
WDH
t
write recovery time
WR
Table 23: LBU write access timing with seperate Read/Write line
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
t
CSWS
t
AWS
t
WRE
t
WDV
Description
t
RTW
t
RAP
17 ns
25 ns
Page
78
t
WCSH
t
WR
t
WAH
t
WDH
Min
Max
0 ns
0 ns
5 ns
12 ns
40 ns
23 ns
0 ns
0 ns
0 ns
0 ns
ERTEC 400 Manual
Version 1.2.2