Siemens ERTEC 200P-2 Manual page 255

Register: FILT_RELOAD_5
Bits: 9dt0
Description:
Register: FILT_RELOAD_6
Bits: 9dt0
Description:
Register: FILT_RELOAD_7
Bits: 9dt0
Description:
Register: FILT_DELAY_0
Bits: 31dt0
Description:
Bit Identifier
3dt0 IN_DELAY_0
7dt4 IN_DELAY_1
11dt8 IN_DELAY_2
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
The division factor reduced by 1 is entered here. Load value 0x000
is converted to 0x001 by the HW.
Reset value:
Load value of clock divider 5
The division factor reduced by 1 is entered here. Load value 0x000
is converted to 0x001 by the HW.
Reset value:
Load value of clock divider 6
The division factor reduced by 1 is entered here. Load value 0x000
is converted to 0x001 by the HW.
Reset value:
Load value of clock divider 7
The division factor reduced by 1 is entered here. Load value 0x000
is converted to 0x001 by the HW.
Reset value:
Reset Attr.
Fh r w
Fh r w
Fh r w
000h
000h
000h
FFFFFFFFh
Function / Description
Selection of clock source for input signal 0:
0x0: CLOCK0
0x1: CLOCK1
0x2: CLOCK2
0x3: CLOCK3
0x4: CLOCK4
0x5: CLOCK5
0x6: CLOCK6
0x7: CLOCK7
0x8 - 0xE: no filtering, only synchronization
0xF: no filtering and no synchronization,
only forwarding
see IN_DELAY_0
see IN_DELAY_0
255
Address: 20h
Attributes: r w
Address: 24h
Attributes: r w
Address: 28h
Attributes: r w
Address: 2Ch
Attributes: r w
ERTEC 200P-2 Manual
Version 1.0