Siemens ERTEC 200P-2 Manual page 346

Enhanced real-time ethernet controller
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5dt4 FRF
6
SPO
7
SPH
15dt8 SCR
Register:
SSPCR1
Bits:
6dt0
SSPCR1 is the control register 1 and contains five different bit fields, which
Description:
control various functions within the PrimeCell SSPMS.
Bit
Identifier
0
RIE
1
TIE
2
RORIE
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
0011 4-bit data
0100 5-bit data
0101 6-bit data
0110 7-bit data
0111 8-bit data
1000 9-bit data
1001 10-bit data
1010 11-bit data
1011 12-bit data
1100 13-bit data
1101 14-bit data
1110 15-bit data
1111 16-bit data
Frame format:
00 Motorola SPI frame format
0h
r
w
01 TI synchronous serial frame format
10 National Mikrowire frame format
11 Reserved, undefined operation
SCLKOUT polarity (applicable to Motorola SPI frame
0h
r
w
format only).
SCLKOUT phase (applicable to Motorola SPI frame
0h
r
w
format only).
Serial Clock rate. The value SCR s used to generate
00h
r
w
the transmit and receive bit range of the PrimeCell
SSPMS.
Reset value:
0h
Reset Attr.
Function / Description
Receive FIFO interrupt enable:
0 =Receive FIFO half-full or more condition does not
0h
r
w
generate the SSPRXINTR interrupt.
1 =Receive FIFO half-full or more condition generates
the SSPRXINTR interrupt.
Transmit FIFO interrupt enable:
0 =Transmit FIFO half-full or less condition does not
0h
r
w
generate the SSPTXINTR interrupt.
1 =Transmit FIFO half-full or less condition generates
the SSPTXINTR interrupt.
Receive FIFO overrun interrupt enable:
0h
r
w
0 =Overrun detection is disabled. Overrun condition
does not generate the SSPRORINTR interrupt.
346
Address:
4h
Attributes:
r
ERTEC 200P-2 Manual
Version 1.0
w

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