Siemens ERTEC 200P-2 Manual page 113

2.3.4.1.3.8 GDMA Status registers
For the monitoring of the GDMA controller via SW, important feedback infor-
mation about the status of the GDMA is the status parameters, contained in
the GDMA Status registers. Six status registers are available:
Job State register (GDMA_JOB_STATUS) indicates via its 32 bits, which
job is active (i.e. started, running or interrupted).
Finished Jobs State register (GDMA_FINISHED_JOBS) contains one "job
finished" bit for each job. This bit is set to "1" each time after the job is
completed. Writing a "1" clears the bit.
Actual Job State register (GDMA_ACTUAL_STATUS) contains 1-bit flag
"Active Job Number Valid" (ACT_JOB_VAL) and 5-bit field "Active Job
Number" (ACT_JOB). Active Job Number indicates the number of the run-
ning job. Bit "Active Job Number Valid" indicates whether the job number is
a valid number, which represents active DMA transfers.
GDMA Interrupt State register (GDMA_IRQ_STATUS) contains a 1-bit "job
finished" bit for each job. This bit is set when a job is finished and a inter-
rupt request (DMA_IRQ) is generated. Writing a "1" clears the bit.
Error State register (GDMA_ERR_STATUS) contains 32 error bits, one bit
for each type of error. The error bit is set to "1" when the corresponding
type of error occurs and when the ERR_INT_EN bit in the GDMA Main
Control register is set to "1". Writing a "1" clears the error bit. If an error bit
is set to "1", then the interrupt request (DMA_IRQ) is generated.
Job counter register (GDMA_JOB_COUNT) counts clock cycles for a se-
lected running job. Selection of the jobs for which the clocks shall be
counted is done with 32-bit register Enable Job Counter for the Job
(GDMA_JC_EN), one of the GDMA Control registers. Reset of the job
counter is done by bit "Reset Job Counter" (JC_RESET) of the GDMA
Main Control register (GDMA_MAIN_CTRL).
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113 ERTEC 200P-2 Manual
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