Apb Decoder; Address Range And Acknowledgement Delay Monitoring; Monitoring At The Ahb Side - Siemens ERTEC 200P-2 Manual

APB Decoder

2.3.2.4.1
The decoder connected to the bridge for addresses and the read data bus enables the
specific PSEL signals to be generated for the individual blocks of the APB bus. It is also
possible to read the various RD data buses of the individual blocks over the decoder on
the AHB bus.
If a PSEL is pending at the APB bus but the address is not within the slave addresses, an
acknowledgement delay (QVZ enable) signal is generated and the address (QVZ ad-
dress) is output. This error is saved externally in the ACCESS error registers of the SCRB
(register SCRB_ACC_ERR_ALL).
The bridge is a slave at the AHB side and the master at the APB side. No error-response
is generated to the AHB side in the case of access with errors at the APB side (posted
behavior). As already indicated above, the instances of erroneous access (address of the
access) are saved in the AHB_APB_ACC_ERR register in the SCRB and an interrupt is
triggered. Erroneous write access is ignored. Erroneous read access returns the value
0x0000_0000.

2.3.2.5 Address Range and Acknowledgement Delay Monitoring

A range of monitoring mechanisms are implemented in the ERTEC 200P for detecting incorrect addressing
and acknowledgement delays (ready delays).

Monitoring at the AHB Side

2.3.2.5.1
Each AHB master (ARM926-D, ARM926-I, PN-IP, GDMA, host IF) is assigned its own
address range monitoring. If an AHB master accesses an address range that is not in
use, the access is acknowledged with an error response and an interrupt IRQ51 (see
2.3.2.14) is triggered in the ARM interrupt controller. The address of the erroneous ac-
cess is also saved in SCRB register QVZ_AHB_ADR and the corresponding access type
(AHB control signals: Read/Write, HBURST, HSIZE) in SCRB register QVZ_AHB_CTRL
(see 2.3.10.9.22).
The master that has triggered the access violation can be read in SCRB register
QVZ_AHB_M.
If RD access at the host IF that has been triggered by parallel (XHIF) or serial (SPI) ac-
cess is acknowledged with an AHB error response, an AHB error IRQ is also triggered at
the event unit (peripheral interface). This entry activates the host interrupt XHIF_XIRQ.
The 3 diagnostic registers QVZ_AHB_ADR/CTRL/M are blocked for subsequent access
violations until the
QVZ_AHB_CTRL
QVZ_AHB_ADR/_CTRL/_M registers remains unchanged. Only a subsequent QVZ up-
dates the QVZ_AHB_ADR/_CTRL/_M registers.
If multiple AHB masters cause an access violation at the same time (within one AHB
clock cycle), only the violation by the highest priority AHB master (prioritization as de-
tailed in 2.3.2.3.1) is displayed.
Important:
If an AHB error response is triggered by the ARM926, this results in a Data/Opcode ille-
gal address interrupt in the ARM926. This interrupt is processed as higher priority by the
ARM926 core.
Address gaps in the APB address range are not visible at the AHB side; the monitoring
mechanisms in 2.3.2.5.2 apply.
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Technical data subject to change
register QVZ_AHB_CTRL
register only, however,
has been
unlocks it;
51
read. Reading
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ERTEC 200P-2 Manual
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