Ertec 200P Data - Siemens ERTEC 200P-2 Manual

1.2 ERTEC 200P data

Manufacturer, technology and package:
Package: FPBGA400, 17 mm x 17 mm, System in Package (SIP)
Operating conditions:
Ambient temperature:
IO supply voltage:
Core supply voltage:
PHY supply voltage:
Power dissipation:
Processor system:
ARM926EJ-S integrated processor system (frequency 125/250 MHz)
16-KByte data and 16-KByte instruction cache
256-KByte instruction/data tightly-coupled memory incl. byte EDC, can be set
in 64-KByte increments (I-TCM: 0 – 256 KByte, D-TCM: 256 – 0 KByte)
Debug compatibility with embedded ICE with JTAG interface, ETM with ETB
(Embedded Trace Buffer)
Memory Management Unit (MMU)
Bus structure:
Internal 32-bit structure
Multi-layer architecture with parallel multimaster to multislaves access structure
(125 MHz)
16/32-bit bus interface to an external SDRAM/SRAM/Flash and external I/O
PROFINET IP:
2 Ethernet ports with integrated PHYs (100 Mb, FD)
IRT High Performance, IRT, RT and NRT data traffic
Interfaces:
External memory controller (EMC), can only be operated at 1.8 V
SDRAM interface (125 MHz)
Asynchronous SRAM interface (4-chip select areas, ready control)
incl. burst flash interface
Host interface (instead of GPIO95-32), can be operated at 1.8 V and 3.3 V
16/32-bit data width
GPIO: GPIO31-0 with 16 I-filters, GPIO95-32 with 64 I-filters in parallel
2
1x I C
2
1x I C (in PN-IP for fiber-optic transceiver)
4x UART including one UART as default without alternate function
2x SPI1 (master / slave,)
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
–40 to +85°C
EMC interface: 1.8V +/-10% (sep. voltage island)
Host interface: 1.8V/3.3 V +/-10% (sep. voltage
isand)
GPIO31..0, ...: 3.3 V +/-10%
1.2 V +/-0.1 V
1.5 V +/-10%
max. 1.2 W (incl. 2x internal PHY)
17 ERTEC 200P-2 Manual
Version 1.0