Siemens ERTEC 200P-2 Manual page 397

8
30 APB_WRITE
31 ERR_LOCK
Register:
Bits:
Description:
Bit Identifier
1dt0 G1: DR_EMC_C
3dt2 G2: DR_EMC_AL
5dt4 G3: DR_EMC_AH
7dt6 G4: DR_EMC_DL
9dt8 G5: DR_EMC_DH
11dt1
G6: DR_EMC_RW
0
13dt1
G7: DR_EMC_PER
2
15dt1
G8: DR_EMC_CLK_SDRAM 3h
4
17dt1
G9: DR_EMC_SDRAM
6
19dt1
G10: DR_EMC_CLK_BF
8
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
xh
xh
DRIVE_EMC
31dt0 Reset value:
SCRB Drive Current of Dedicated Signals (1.8V)
Each GPIO bit is set to the drive current on the basis of the
following coding
-----1.8V--------
00 - 4 mA
01 - 6 mA
10 - 8 mA
11 - 12 mA
and clock enable/disable for BF and SDRAM
Reset
3h
3h
3h
3h
3h
3h
3h
3h
3h
397
word access is permitted
0: Read access
r
w
h 1: Write access
Set to '1' by the HW if
erroneous SCRB access is detected.
Further HW entries are
r
w
then blocked.
h
The SW must reset the bit to '0' to
enable new entries.
Address: 78h
FFFFFF Attribu-
h tes:
Attr. Function / Description
r w Signal list: DTXR, XOE_DDRIVER
r w Signal list: A14 - A0
r w Signal list: A23 - A15
Signal list: D15 - D0, XBE0_DQM0,
r w
XBE1_DQM1
Signal list: D31 - D16, XBE2_DQM2,
r w
XBE3_DQM3
r w Signal list: XWR, XRD
r w Signal list: XCS_PER0 - 3
Signal lists:CLK_O_SDRAM0,
r w
CLK_O_SDRAM1, CLK_O_SDRAM2
Signal list: XCS_SDRAM,
r w XRAS_SDRAM, XCAS_SDRAM,
XWE_SDRAM
r w Signal list: CLK_O_BF0 - 2
r w
ERTEC 200P-2 Manual
Version 1.0