Siemens ERTEC 200P-2 Manual page 188

- Write access (HOSTIF-AHB master) by the external host
- The ARM926EJ-S must not change the XHIF configuration (data width, ready polarity or
command mode)
once the external host has started write access.
The XHIF_XRDY signal is implemented as a bidi buffer. However, the output driver only
becomes active with an XHIF CS, i.e. other devices can actively pull the signal when
there is no access with XHIF. This basically provides open drain functionality.
XHIF_XRDY must be pulled to "normally ready" with an external pull resistor, i.e. pull-up
if XHIF_XRDY = high-active and pull-down if XHIF_XRDY = low-active, so that at the end
of access the XHIF_XRDY signal can also be recognized by an external host operating
with a lower clock rate that the ERTEC 200P (background: XHIF_XRDY is only actively
driven by the XHIF module for one clock cycle).
The XHIF_XRDY signal sends a ready message to the external XHIF host. XHIF_XRDY
is implemented with a tristate driver whose Output_Enable does not become active until
the start of access (as soon as CS and RD or WR are active) and becomes inactive again
at the end of access (one clock cycle after active XHIF_XRDY).
For module design, please note that XHIF_XRDY is a controlled push-pull output which
requires an external pull resistor in accordance with its polarity (i.e. pull-down if
XHIF_XRDY is low-active and vice versa). The pull resistor ensures that XHIF_XRDY is
pending at the external host for long enough.
When configuring the external host, please note that XHIF_XRDY briefly appears to the
host as active at the start of access because of the pull resistor (it takes up to 11 ns for
the pin to be driven by ERTEC 200P). To prevent the external host from interpreting ac-
cess as acknowledged at this stage, there must be a delay before it evaluates
XHIF_XRDY. When the external host is an ERTEC 200P, this delay would for example
be implemented by configuring the appropriate number of "Read/Write Strobe Cycles" in
the EMC interface (R_Strobe or W_Strobe parameter in the ASYNC_BANK0-3 EMC
registers).
How does the host detect that the ERTEC 200P is ready for host access after the reset
phase?
The host recognizes that the ERTEC 200P is ready for host access with the CS_R Page
0 range and offset registers. Page 0 range and offset registers have the default value
0x0000_0000; after configuration by ERTEC 200P, the registers of page 0 must contain
values of 0x0000_0000.
This means that the host must poll these registers in the CS-R area after an ERTEC
200P reset until the values initialized by the ERTEC 200P are read; the host is then able
to recognize that the ERTEC 200P is ready for host access.
Can deadlock occur during host access?
Problems can only occur during the active reset phase of the ERTEC 200P. They may for
example be triggered by a:
- Software reset
- Watchdog reset
If the host accesses the CS_M area during the reset phase, access by ERTEC 200P will
not be completed with READY. Access by the host to CS_R is completed during the reset
phase, in other words there are no problems there.
Please note the following points to detect / avoid the problem:
- The host must detect an ERTEC 200P reset (at the host, use a GPIO
that signals the reset state) and block access to CS_M
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
188 ERTEC 200P-2 Manual
Version 1.0